1. Field of the Invention
The present invention relates to semiconductor devices incorporating electrodes consisting of a layer of polysilicon covered by a self-aligned layer of metal silicide.
2. Description of the Related Art
As line widths and geometries for semiconductor devices are made smaller, the polysilicon electrodes that form the gates of MOS devices and wiring lines within semiconductor devices become undesirably resistive. Multilayer electrodes in which a layer of polysilicon is covered by one or more layers of metals or metal silicides are used to provide electrodes having a lower resistance than electrodes consisting solely of polysilicon. Silicide electrodes may consist, for example, of a layer of polysilicon having a thickness of approximately 1000 .ANG. to 3000 .ANG. covered by titanium suicide or another metal silicide to a thickness of greater than 100 .ANG.. The silicide layer on the polysilicon layer acts as a lower resistance conduction path in parallel with the polysilicon layer over the entire length of the gate electrode. While it has become important to provide reduced conductivity gate electrodes in high density integrated circuit devices, there have been significant difficulties in implementing this technology in a reliable manner that predictably achieves high levels of performance.
A typical implementation of a multilayer, silicide on polysilicon electrode is the so-called self-aligned suicide ("salicide") structure, aspects of which are illustrated schematically in FIGS. 1-4. The illustrated MOS devices are formed on a P-type substrate 10 and include, for example, thick field oxide regions to provide isolation from other, adjacent MOS devices. As is conventional, the device isolation structures may be formed by a local oxidation of silicon (LOCOS) process or one of the modified LOCOS processes. Often, however, device isolation is provided by a shallow trench structure formed by etching a trench into the substrate and refilling the trenches with a deposited insulator, such as chemical vapor deposited (CVD) oxide. A gate oxide layer 12 is formed by thermal oxidation over the active device region between the device isolation structures and a polysilicon gate electrode 14 is formed on the gate oxide layer 12. The polysilicon gate electrode 14 is formed by depositing a layer of undoped polysilicon over the substrate, typically using low pressure chemical vapor deposition (LPCVD), implanting impurities into the polysilicon and annealing to activate the impurities and to render the polysilicon conductive. The polysilicon layer is patterned using conventional photolithography. Polysilicon wiring lines are typically formed elsewhere on the integrated circuit device at the same time and in the same manner as gate electrode 14 is formed.
Doped source/drain regions 16, 18 are formed on either side of the polysilicon gate electrode to define the channel region of the illustrated MOS field effect transistor. Generally, a lightly doped drain (LDD) structure is used in small design rule MOS transistors of the type that are frequently used in modem memory and logic devices. LDD source/drain regions are typically formed in a two step process, beginning with a relatively low level implantation of dopants made self-aligned to polysilicon gate electrode 14 to form the structure illustrated in FIG. 1. Subsequently, insulating sidewall spacer structures 20 (FIG. 2) arc formed on either side of the gate electrode by first depositing a layer of CVD oxide over the FIG. 1 structure and then anisotropically etching back the oxide layer to expose the substrate over the lightly doped source/drain regions 16, 18. Etching back the CVD oxide layer produces the spacer oxide structures 20 on either side of the polysilicon gate electrode 14. This process also provides spacer regions along the sides of the polysilicon wiring lines, if the wiring lines arc exposed during the oxide deposition and etch back process. After the spacer oxide regions 20 are provided on either side of the polysilicon gate electrode 14, a second, heavier ion implantation is made into the source/drain regions 22, 24 self-aligned to the spacer oxide regions 20.
Integrated circuit devices typically include both polysilicon gate electrodes, like gate electrode 14 shown in FIG. 2, and polysilicon wiring lines (not shown) which connect gate electrodes to other circuits and which provide other connections in the integrated circuit device. For smaller line widths, even highly doped polysilicon is sufficiently resistive to diminish the performance of MOS and other types of integrated circuits which include polysilicon electrodes or which are connected by polysilicon electrodes, due to decreased signal levels and longer RC time constants. To reduce the resistance of conventional polysilicon gate electrodes and wiring lines, further processing of the FIG. 2 device continues to convert the polysilicon gate electrodes and wiring lines into silicide structures using self-aligned silicide (salicide) techniques. Although a variety of different silicides are known to be acceptable, the silicide most commonly used at this time is titanium silicide, and that structure is described herein. Titanium silicide layers are formed on the polysilicon electrodes and wiring lines and select portions of the substrate, if desired, by first sputtering a layer of titanium over the surface of the device to a thickness of, for example, 500 .ANG.. This titanium layer is converted into titanium silicide at the surface of the polysilicon gate electrodes and wiring lines and at the exposed portions of the substrate, including the source/drain regions 22, 24, in a two step process. In the first process step, the device is subjected to a rapid thermal anneal (RTA) by heating the device to a temperature of up to about 700.degree. C. for about thirty seconds. The first RTA step converts the titanium layer into titanium silicide (nominally TiSi.sub.2) anywhere the titanium layer is in contact with a silicon (crystalline or polycrystalline) surface. The device is then etched using a wet etch consisting of H.sub.2 O.sub.2 and NH.sub.4 OH diluted in water to remove unreacted titanium from the surface of the device and exposing the oxide regions of the device. A layer of titanium silicide 26 (FIG. 3) or 34 (FIG. 4) is left over the polysilicon gate electrode 14 and over the wiring line 18. When the source/drain regions 22, 24 are exposed during the silicidation process, titanium suicide regions 28, 30 are also formed on the surfaces of the source/drain regions 22, 24. Such titanium silicide regions 28, 30 are often preferred, particularly for logic devices, because silicided source/drain regions provide lower sheet resistance within the source/drain regions and provide better contacts to the source/drain regions 22, 24. Silicided contacts on the source/drain regions are thus preferred so long as the amount of silicon consumed in the silicidation process does not alter the transistor performance or result in excessive junction leakage at the source/drain regions.
After the unreacted titanium is etched from the device, further processing is necessary to provide suitable silicide layers on the gate electrodes and wiring lines of the device. The first step of the two step annealing process described to this point forms a relatively high resistivity phase of titanium silicide on the silicon surfaces, so that the illustrated salicide structure does not have as low a level of resistivity as is desirable. It is accordingly necessary to expose the device to a second step--a second rapid thermal anneal at a temperature in excess of 800.degree. C. for at least ten seconds--to convert the titanium suicide to the lower resistivity phase of titanium silicide. The device is then subjected to further processing to complete fabrication.
A number of the processing steps necessary to the formation of salicide structures are critical. For example, if the temperature control is poor for the initial RTA step of converting the titanium in contact with silicon to titanium silicide, e.g., if the temperature for the initial anneal is near 800.degree. C., then there may be rapid silicon transport laterally through the titanium layer, which could convert titanium to titanium silicide in undesirable regions spaced away from the silicon surfaces. For example, if the temperature in the initial anneal is close to 800.degree. C., silicon is transported along the portion of the titanium layer extending over the oxide spacers 20 on either side of the gate electrode 14, forming "stringers" 32 between the gate electrode and the source/drain regions 22, 24 that are not removed in the conventional salicide process. Such stringers bridging between the gate silicide layer 26 and the source/drain silicide regions 28, 30 are indicated by reference numeral 32 in FIG. 3. The formation of the stringer 32 in the FIG. 3 structure is obviously undesirable in that it shorts the gate to the source/drain region and renders the transistor inoperative. The high speed at which titanium is transported through polysilicon at the annealing temperatures required to obtain the low resistivity (C54) phase of titanium silicide mandates that the two step annealing process described above be employed. Use of the two step process produces a salicided FET such as that show in FIG. 4 in a process that exhibits a lower probability of bridging problems.
Practice of the two stage process which produces the device of FIG. 4 has disadvantages, however. As a practical matter, use of a single annealing step at a temperature of about 800.degree. C. to directly produce the low resistivity phase of titanium silicide in a one step process is a far more reliable way of producing low resistivity gate electrodes than the two step process. Thus, while the FET illustrated in FIG. 3 is essentially useless in practice, there is a much better likelihood that the one step process indicated by FIG. 3 will produce a low resistivity gate electrode than the two step process used for making the FIG. 4 electrode. This is particularly true for narrow gate electrodes and wiring lines. It becomes increasingly difficult to form acceptable low resistivity salicide electrodes and wiring lines according to the FIG. 4 process when these structures are made using polysilicon lines that are less than one half micron across. In particular, the resistivity of gate electrodes and wiring lines rises precipitously for line widths of less than one half micron. The increase in the resistivity for smaller line widths reflects the fact that the second annealing step conventionally used to produce the low resistivity phase of suicide can be ineffective for such narrow line widths.
A comparison of FIGS. 3 and 4 illustrates a mechanism that is believed to impede the conversion of silicide layers formed on narrow line width polysilicon layers to the low resistivity silicide phase. FIG. 3 shows a titanium silicide layer 26 formed in the generally unacceptable single step annealing process that uses a comparatively uncontrolled initial silicidation process to form a salicide layer 26 which extends deeply into the surface of the illustrated polysilicon gate electrode. The less controlled initial growth process used in forming the FIG. 3 FET tends to produce a gate electrode that has a low resistivity which is desirable regardless of the fact that the FIG. 3 structure is otherwise undesirable. The present inventors have observed that the two step annealing process used in forming the FIG. 4 structure more typically forms a thinner and more constrained titanium silicide layer 34 on the polysilicon gate electrode 14, as illustrated in FIG. 4. Near the edge of the polysilicon gate electrode 14, the gate oxide spacers 20 appear to "clamp" the edges of the titanium silicide layer 34, limiting the growth of the titanium silicide layer which, if not clamped, would have expanded to a thickness greater than the thickness of silicon consumed during the titanium silicide growth process. Titanium silicide grows most freely near the center of the FIG. 4 gate electrode so that the thickest part of the titanium silicide layer 34 is formed above the center of the polysilicon gate electrode 14. Titanium silicide along the edges of the layer 34 has a high level of stress, as initially formed in the first step of the two step annealing process, while the more central portion of the titanium silicide has a comparatively lower level of stress. By contrast, the titanium silicide layer 26 of FIG. 3 has a lower level of stress throughout its width because the low resistivity phase of titanium silicide is formed in the initial annealing step in a comparatively unconstrained manner. If the width of the titanium silicide layer 34 formed in the FIG. 4 process is sufficiently small, then a considerable level of stress will exist even at the center of the titanium silicide layer 34 even after completion of the annealing processes. If too high of a stress level exists across the entire titanium silicide layer as it is formed, then a subsequent annealing step is not successful in converting enough of the titanium silicide layer 34 to the low resistivity phase and so may not reduce the resistivity of the gate electrode in the desired manner. A salicide structure in which the as grown silicide layer has too high of a level of stress may thus produce an undesirably resistive salicide structure which is poorly suited for use as a gate electrode or a wiring line. As such, the silicide layer 26 formed in FIG. 3 is more desirable than the thinner more stressed layer 34 of FIG. 4. On the other hand, the method used for forming FIG. 3 structure is typically unacceptable because of its propensity for bridging, despite the lower gate electrode resistivities achieved through practice that method.
For smaller device geometries, gate electrodes and wiring lines are narrower and it is increasingly more necessary to reduce the resistivity of gate electrodes and wiring lines within memory and logic devices. On the other hand, it is increasingly more difficult to form appropriate salicide electrode structures for narrower gate electrodes and wiring lines. In particular, it is difficult to provide the low resistivity phase of titanium silicide for narrow line width gate electrodes and wiring lines. It is accordingly desirable to develop better designs and more robust processing techniques for forming low resistance salicide structures.